This invention relates to a dynamic gate array for use in simulating operation of a logic circuit composed of an assembly or combination of a plurality of various gates. The assembly is, for example, what is to be implemented as wired logics in a custom LSI.
A dynamic gate array serves as an effective tool in simulating a combination of logic operations and in designing an assembly of gates for which the logic operation is not yet ultimately decided.
Custom LSI's are useful in reducing the size and price of hardware devices composed of logic circuits. New custom LSI's are therefore often designed in consideration of the hardware devices which are to be developed. It is, however, impossible to change or amend the logics which are once implemented or wired in a custom LSI as wired logics. A tool which makes it readily possible to change the logics, is therefore eagerly desired on trially manufacturing or simulating those hardware devices for which the logics are not yet settled.
Examples of the tool now available on designing hardware devices are IC's, programmable logic arrays, gate arrays, and the like. The IC's are assembled or combined so as to actually implement a hardware device. The logics are changed as desired. The actual implementation is, however, troublesome. Alteration of the logics is time consuming. The programmable logic array must be manufactured afresh on changing the logics. Moreover, the programmable logic array can not implement a hardware device on a large logic scale. The gate array must also be fabricated anew on amending the logics. It is expensive to manufacture new gate arrays.
Software simulations have also been tried instead of such hardware tools. It is, however, impossible with the software simulation to inspect the whole logics when the simulation is carried out for partial logics on a small logic scale. Simulation must therefore be carried out for appreciably large-scale modules and, in an extreme case, for the whole device. At any rate, the simulation must actually be carried out in sequence for individual logic operations of the whole device. The sequential simulation results in a long simulation time, which is intolerably long in practice.
It has therefore been desired to provide a hardware tool for use in simulating an assembly of gates before settlement of the logics. The hardware tool must be capable of carrying out the simulation in a shortest possible time. As described in patent application Ser. No. 513,489 filed July 13, 1983, by Tohru Sasaki with claim to the Convention Priorities based on three patent applications filed in Japan under patent application Ser. Nos. 121,599, 121,600, and 177,073, all of 1982, such a hardware tool is useful also in a logic simulator for use in simulating an overall operation of a logic device which may be an electronic digital computer comprising a central processing unit, a main memory, a cache memory, and microprogram memories.